Aspects of the present invention are related to subject matter disclosed in co-pending applications entitled xe2x80x9cDielectric Interposer for Chip to Substrate Soldering,xe2x80x9d Attorney Docket No. FI9-98-129, and xe2x80x9cUnderfill Preform Interposer for Joining Chip to Substrate,xe2x80x9d Attorney Docket No. FI9-97-215 filed on even date herewith and assigned to the assignee of the present invention.
1. Field of the Invention
This invention relates to the manufacture of electronic modules, namely flip chip packaging, utilizing an improved method of assembling the module. The improved method allows for enhanced contact with less stressing on the solder joints used to electrically interconnect a chip and a substrate resulting in an electronic module having higher integrity and reliability.
2. Description of Related Art
Multi-layer ceramic electronic components are typically joined together by soldering pads on a surface of one of the electronic components to corresponding pads on the surface of the other component. Controlled Collapse Chip Connection is an interconnect technology developed by IBM as an alternative to wire bonding. This technology is generally known as C4 technology or flip chip packaging. Broadly stated, one or more integrated circuit chips are mounted above a single or multi-layer ceramic substrate and pads on the chip are electrically and mechanically connected to corresponding pads on the substrate by a plurality of electrical connections such as solder bumps. The integrated circuit chips may be assembled in an array such as a 10xc3x9710 array on the multi-layer ceramic surface.
One of the key features in using flip chip packaging is the ability to accommodate a considerable distortion in pattern between the chip and the substrate. This accommodation is due to a self-alignment capability produced by surface tension minimization of the solder joints. What cannot be tolerated, however, is any significant deviation from planarity between the chip surface and the substrate surface since electrical interconnection cannot occur unless the solder bump on the chip physically contacts the substrate.
Multi-layer ceramic (MLC) chip carriers with flip chip technology often possess, due to design, the tendency to have localized bulges at the location of underlying substrate vias. In addition, residual camber (non-planarity) from sintering the substrate can lead to further non-planarity across the chip site. A camber magnitude much greater than about 25 to 30 microns will lead to non-contact opens after a chip join attempt. Thus, it is desirable to find a way of overcoming the non-planarity typically found on a chip and substrate used in flip chip packaging resulting in better solder interconnections.
U.S. Pat. No. 5,587,337 to Idaka et al. discloses a method of manufacturing bump electrodes with a larger top surface area than bottom surface area. Both surfaces are flat which would not overcome the non-planarity of a chip and substrate when joining such components in flip chip packaging.
U.S. Pat. No. 5,527,734 to van der Putten discloses a method of forming solder interconnections having a truncated pyramid shape. The truncated pyramidal shape of the solder is formed using an electroless metallization bath. This reference neither suggests nor discloses a method of overcoming the non-planarity of components in flip chip packaging. The flat top surface of the solder would not overcome the non-planarity of the electronic components in an electronic module.
U.S. Pat. No. 5,478,007 to Marrs discloses a method and structure for flip chip interconnection of a chip to a substrate utilizing a ball bond having a conical section and a base section. The disclosure includes a number of additional steps in forming the ball bond which add to an already cumbersome process. The reference neither suggests nor discloses a method of overcoming the non-planarity of the electronic components in a module.
U.S. Pat. No. 5,244,143 to Ference et al. (and assigned to the assignee of the present invention) discloses an apparatus and method of injection molding solder mounds onto electronic devices. This reference neither suggests nor disclose a method of overcoming the non-planarity of the electronic components when assembling electronic modules.
U.S. Pat. No. 4,751,563 to Laibowitz et al. discloses an interconnect with a contamination resist cone formed on a substrate. This reference neither suggests nor discloses a method or apparatus for overcoming the non-planarity of electronic components when assembling electronic modules.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide a method of overcoming the non-planarity of electronic components used in assembling electronic modules.
It is another object of the present invention to provide a method of assembling electronic modules having improved solder interconnections.
It is yet another object of the present invention to provide a solder preform which overcomes the problem of camber on electronic components used in flip chip packaging.
A further object of the invention is to provide an electronic module having improved reliability, integrity and less prone to electrical failure of solder interconnections.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.
The above and other objects and advantages, which will be apparent to one of skill in the art, are achieved in the present invention which is directed to, in a first aspect, a process for forming non-spherical shapes in solder interconnects on the surface of a substrate or a semiconductor die comprising the steps of: (a) depositing a first layer of solder onto a surface; (b) depositing a second layer of solder over the first layer of solder; and (c) forming the first and second layers of solder into a non-spherical shape, wherein the non-spherical shape of the solder interconnects facilitate joining between two surfaces.
Preferably, step (b) comprises depositing a second layer of solder having a lower melting temperature than the first layer of solder.
Preferably, step (c) comprises molding the first and second layers of solder into a non-spherical shape with a coining die comprising a rigid, non-solder wettable plate having an array of non-spherically shaped cavities, the die being heated to an elevated temperature. More preferably, step (c) comprises molding the plurality of solder interconnects with a heated coining die comprising a rigid, non-solder wettable plate having an array of non-spherically shaped cavities such that the coining die deforms the second layer of solder into a non-spherical shape. Most preferably, step (c) comprises molding the first and second layers of solder into a non-spherical shape, a portion of the non-spherical shapes comprising stand-offs.
The present invention relates to, in a second aspect, a process for forming non-spherical shapes in solder interconnects comprising the steps of: (a) providing a semiconductor wafer and a substrate for mounting the wafer; (b) applying a masking layer to the wafer or to the substrate; (c) patterning and developing a plurality of openings in the masking layer; (d) forming a plurality of solder interconnects by plating a layer of solder into the plurality of openings in the masking layer; and (e) molding the plurality of solder interconnects into a non-spherical shape, wherein the non-spherical shape of the plurality of solder interconnects facilitates joining of the wafer and the substrate in a non-planar environment.
The process may further include the step of applying a blanket seed layer to the wafer prior to step (b) wherein the step of applying a blanket seed layer to the wafer comprises applying a layer of chromium-copper alloy or a layer of titanium-copper alloy to the wafer. The seed layer not covered by the solder interconnects may be removed prior to step (e).
Preferably, step (b) comprises applying a photoresist to the wafer.
Preferably, step (d) comprises forming a plurality of solder interconnects by plating a first and second layer of solder into the plurality of openings in the masking layer. More preferably, the first layer of solder has a thickness of about 0.1 to 0.13 mm. More preferably, the second layer of solder has a thickness of about 0.02 to 0.025 mm. Even more preferably, step (d) comprises forming a plurality of solder interconnects wherein the first layer of solder has a thickness of about 0.1 to 0.13 mm and a diameter of about 0.1 to 0.13 mm and the second layer of solder has a thickness of about 0.02 to 0.025 mm.
The process may also comprise, in step (d), forming a plurality of solder interconnects by plating a first and second layer of solder into the plurality of openings in the masking layer wherein the first layer of solder comprises a higher melting solder than the second layer of solder. Preferably, the process may further include the steps of molding the plurality of solder interconnects into a conical shape, contacting the wafer with the substrate and reflowing the second layer of solder to facilitate joining of the wafer and the substrate.
Step (d) may comprise forming a plurality of solder interconnects by plating a first layer of solder comprising a lead-tin alloy into the plurality of openings in the masking layer. Step (d) may also comprise forming a plurality of solder interconnects by plating a second layer of solder comprising a tin alloy into the plurality of openings in the masking layer. Preferably, the tin alloy is selected from the group consisting of eutectic tin-lead, tin-bismuth, and tin-indium. Most preferably, step (d) comprises forming a plurality of solder interconnects by plating a first layer of solder comprising a lead-tin alloy and a second layer of solder comprising a tin alloy into the plurality of openings in the masking layer.
Preferably, step (e) comprises molding the plurality of solder interconnects into a conical shape, and even more preferably, wherein the first layer of solder has a base angle of about 75 to 80 degrees and the second layer of solder has a base angle of about 65 to 70 degrees.
Preferably, step (e) includes molding the plurality of solder interconnects into a first non-spherical shape and a second non-spherical shape wherein the second non-spherical shape has a flat top for stand-offs.
Preferably, step (e) comprises molding the plurality of solder interconnects into a non-spherical shape with a heated coining die comprising a rigid, non-solder wettable plate having an array of non-spherically shaped cavities wherein the heated coining die deforms the plurality of solder interconnects into a non-spherical shape. Most preferably, the plate of the coining die comprises a material selected from the group consisting of glass, molybdenum alloy, titanium alloy, titanium-tungsten alloy, nickel alloy and stainless steel.
Preferably, step (e) comprises molding the plurality of solder interconnects with the coining die into a cone shape. Most preferably, step (e) comprises molding a first portion of the plurality of solder interconnects into a non-spherical shape and a second portion of the plurality of solder interconnects to form stand-offs with a coining die having non-spherically shaped cavities and stand-off shaped cavities.
The process may further include the step of contacting the wafer with the substrate. Preferably, the step of contacting the wafer with the substrate comprises reflowing the solder interconnects to facilitate joining of the wafer and the substrate. Most preferably, the step of joining the wafer and the substrate is adapted to accommodate up to about 50 microns of camber on the substrate.
Preferably, during the step of reflowing the solder interconnects, a portion of the solder interconnects are stand-offs having a flat surface with a height less than the non-spherically shaped solder interconnects such that the stand-offs limit the extent of collapse of the cone shaped solder interconnects during reflow. Most preferably, during the step of reflowing the solder interconnects, the standoffs are about 25 to 40 microns shorter than the solder interconnects such that the extent of collapse of the cone shaped solder interconnects during reflow is limited. Even more preferably, the plurality of solder interconnects comprises a first layer of solder and a second layer of solder, the first layer of solder having a higher melting temperature than the second layer of solder, and wherein the step of ref lowing occurs at the melting temperature of the second layer of solder.
The process may further include the step of forming stand-offs comprising polyimide on the semiconductor wafer.
In another aspect, the present invention is directed to a process for forming cone shaped solder on a semiconductor wafer or a substrate for use in controlled chip collapse connections comprising the steps of: (a) providing a first surface; (b) applying a bond pad for a connection to the surface; (c) applying a seed layer over the surface; (d) applying and patterning a masking layer over the seed layer to form an opening in the masking layer exposing the seed layer; (e) plating a metal solder into the opening of the masking layer; (f) stripping the masking layer; (g) removing the seed layer not covered by the solder; and (h) molding the solder to form a cone shape.
Preferably, step (a) comprises providing a semiconductor surface or a substrate surface; step (b) comprises applying a bond pad comprising layers of silicon oxide, chromium and copper; step (c) comprises applying a layer of chromium/copper alloy or titanium/copper alloy over the surface; and step (d) comprises applying and patterning a photoresist layer over the seed layer to form an opening in the masking layer exposing the seed layer.
Preferably, step (e) comprises plating a first solder followed by plating a second solder, and, most preferably, wherein the second solder has a lower melting temperature than the first solder. Even more preferably, step (e) comprises plating a first solder comprising a 97% lead/3% tin alloy followed by plating a second solder comprising a eutectic tin/lead alloy.
Preferably, step (h) comprises molding the solder to form a cone shaped wherein the cone shape has a taper about 15 to 25 degrees from the vertical. More preferably, step (h) comprises molding the solder with a coining die to form the cone shaped solder. The coining die may comprise a rigid, non-solder wettable plate having an array of conically shaped cavities. Preferably, step (h) comprises molding the solder with a heated coining die comprising a rigid, non-solder wettable plate having an array of conically shaped cavities. Most preferably, step (h) comprises molding the solder with a coining die comprising a rigid, non-solder wettable plate having conically shaped cavities and trapezoidally shaped cavities. The coining die molds a portion of the solder into trapezoidal shapes as stand-offs wherein the stand-offs control the collapse of the solder during contact between a semiconductor wafer and a substrate.
Preferably, step (e) comprises plating a first solder followed by plating a second solder having a lower melting temperature than the first solder into the opening of the masking layer and step (h) comprises molding the first and second solders with a heated coining die comprising a rigid, non-solder wettable plate having an array of conically shaped cavities. More preferably, the heating element of the coining die deforms the second solder to form the conical shape.
The process may further include the step of forming polyimide standoffs, and wherein the polyimide standoffs are formed on a semiconductor surface or a substrate surface.
In yet another aspect, the present invention is directed to a method of joining semiconductor chips and substrates in a non-planar environment using non-spherically shaped solder comprising the steps of: (a) providing a semiconductor chip and a substrate for mounting the chip; (b) forming a plurality of non-spherical solder interconnects on a surface of the chip or substrate; (c) forming standoffs on a surface of the chip or the substrate; and (d) contacting the chip with the substrate, whereby the placement force is reduced and the standoffs limit the extent of collapse of the solder interconnects.
The process may further include, prior to step (b), the step of applying and patterning a photoresist to the surface of the chip or the substrate on which surface the solder interconnects are formed.
Preferably, step (b) further comprises the steps of: plating a first solder on a surface of the chip or the substrate; plating a second solder over the first solder; and molding the solders with a heated coining die comprising a rigid, non-solder wettable plate having an array of non-spherically shaped cavities such that the heated coining die deforms the second solder to form the non-spherical shape. More preferably, the first layer of solder comprises a higher melting point solder than the second layer of solder. Even more preferably, the first layer of solder comprises a lead-tin alloy and the second layer of solder comprises a tin alloy.
Preferably, the step of contacting the chip to the substrate occurs at an elevated temperature greater than room temperature but less than the solder reflow temperature.
Preferably, the non-spherical shape is conical, and most preferably, the conical shape of the solder interconnect has a base angle of about 75 to 80 degrees.
The plurality of solder interconnects and the standoffs can be formed on a surface of a chip or a substrate.
In still yet another aspect, the present invention is directed to a method of joining semiconductor chips and substrates in a non-planar environment using non-spherically shaped solder comprising the steps of: (a) providing a semiconductor chip and a substrate for mounting the chip; (b) forming a plurality of non-spherical solder interconnects on a surface of the chip; (c) forming standoffs on a surface of the chip or substrate; and (d) contacting the chip with the substrate, whereby the placement force is reduced and the standoffs limit the extent of collapse of the solder interconnects.
In a further aspect, the present invention is directed to a method of joining semiconductor chips and substrates in a non-planar environment using non-spherically shaped solder comprising the steps of: (a) providing a semiconductor chip and a substrate for mounting the chip; (b) forming a plurality of non-spherical solder interconnects on a surface of the substrate; (c) forming standoffs on a surface of the chip or the substrate; and (d) contacting the chip with the substrate, whereby the placement force is reduced and the standoffs limit the extent of collapse of the solder interconnects.
In yet another aspect, the present invention is directed to a semiconductor substrate having at least one electrical element formed thereon, the substrate comprising at least one bonding pad disposed on the substrate corresponding to the electrical element; and a cone shaped solder interconnect on the bonding pad adapted for electrical and mechanical connection to the electrical element.
In a final aspect, the present invention relates to a semiconductor chip having at least one electrical element formed thereon, the chip comprising at least one bonding pad disposed on the substrate corresponding to the electrical element; and a cone shaped solder interconnect on the bonding pad adapted for electrical and mechanical connection to the electrical element.